The present invention relates to compensation circuits, and in particular, to cascode compensation circuit and method for amplifier stabilization.
Stability of operational amplifiers, as well as other circuits which may apply feedback, depend on the transfer function of the amplifier circuit. Reactive elements such as capacitors within the amplifier circuit may cause changes in impedances and phase delays in signals propagating through the amplifier circuit. These impedance changes may change amplifier gain and the phase of signals propagating through the circuit as a function of signal frequency.
As signal frequency increases, at some frequency F0, amplifier gains typically fall below unity gain (i.e. below 0 dB) and remain below unity for all frequencies greater the F0. An amplifier circuit that utilizes negative feedback is stable when the open loop phase change associated with F0 is substantially above −180 degrees at unity gain. The phase margin is the difference between the phase associated with F0 and −360 degrees. Accordingly, phase margin is one way of quantifying the stability of an amplifier circuit.
Many amplifier circuits are designed for a target capacitive load. These circuits may be tuned to give a sufficient phase margin to remain stable over a designed bandwidth. The transfer function of the amplifier circuit may change depending on the capacitive load. In some cases, the capacitive load is not exactly the targeted capacitive load and the actual capacitor load may degrade the phase margin of the amplifier circuit and cause peaking in the frequency response. This peaking may degrade the power supply rejection ration (PSRR). Sometimes the capacitive load varies due to part manufacturing variations, for example.
FIG. 1 illustrates an example prior art circuit 100 with cascode compensation. Circuit 100 includes transconductance amplifier 101, resistor R1, resistor R0, capacitor C1, capacitor Co, capacitor CA, transistors 101-106, and current source 104 configured as shown. In this example, circuit 100 uses Ahuja compensation. Ahuja compensation is a cascode compensation scheme used in some amplifier circuits to improve the bandwidth over the well known Miller compensation method. Ahuja compensation boosts the transconductance (gm), and the second pole of its transfer function is moved forward to increase stability. For instance, circuit 100 includes a cascode transistor 103 coupled to capacitor CA that provides cascode compensation. The cascode compensation allows amplifier circuit 100 to remain stable for a limited range of values of output capacitor C0. However, as illustrated in FIGS. 2 and 3 below, variations in output capacitances outside the above-mentioned range can lead to problems using the prior art circuit.
FIG. 2 illustrates bode plot 200 and a root locus plot 210 of an exemplifying embodiment of the cascoded compensation loop inside the prior art amplifier circuit 100 of FIG. 1 designed in this example to be stable with an output capacitor C0 value of 50 pF. The bode plot 200 includes a gain response 201 and a phase response 202. The behavior of a cascode compensation circuit may be understood by analyzing the open loop gain and associated poles. The open loop gain is as follows:
                                          A            V                    =                                    -                                                                    gm                    2                                    ⁢                                      R                    0                                                                    (                                      1                    +                                                                  sR                        0                                            ⁢                                              C                                                  EQ                          ⁢                                                                                                          ⁢                          0                                                                                                      )                                                      ×                                          sC                A                                            1                +                                  s                  ⁢                                                            C                      EQA                                                              gm                      A                                                                                            ×                                          R                1                                            1                +                                                      sR                    1                                    ⁢                                      C                    1                                                                                      ,                            (                  EQ          .                                          ⁢          1                )            where,
            C      EQA        =                            C          A                ⁢                  C          0                                      C          A                +                  C          0                      ,            C              EQ        ⁢                                  ⁢        0              ≅                  C        0            +              C        A              ,and the poles are zeros are as follows:
            z      1        =    0              P      1        =          -              1                              R            1                    ⁢                      C            1                                          P      2        =          -              1                              R            0                    ⁢                      C                          EQ              ⁢                                                          ⁢              0                                                      P      3        =          -                        gm          A                          C          EQA                    The poles and zero above are illustrated in FIG. 2, where the low frequency gain AA and the GBW_Extrapolated are also illustrated:
                    A        A            =                                    gm            2                    ⁢                      R            0                    ⁢                      C            A                                    C          A                      ,    and              GBW      Extrapolated        =                            A          A                ⁢                  P          2                    =                                    gm            2                    ⁢                      C            EQA                                                C                          EQ              ⁢                                                          ⁢              0                                ⁢                      C            1                              
A frequency indicated by line 203 shows a point 204 where the gain response 201 crosses 0 dB and point 205 shows the corresponding phase. Bode plot 200 shows a phase margin of 70 degrees (PM=70°) at 205. The root locus plot 210 shows the movement of the poles and zeros as the loop is closed. The poles and zeros remain on the real axis, and therefore the system is stable at C0=50 pF.
If P3>>P2 as in the example of FIG. 2, then the loop gain equation (EQ. 1) is a good estimation of the more general equation (EQ. 2) as follows:
                              A          V                =                  -                                                    gm                2                            ⁢                              R                0                            ⁢                              R                1                            ⁢                              sC                A                                                                    (                                  1                  +                                                            sR                      1                                        ⁢                                          C                      1                                                                      )                            ⁡                              [                                  1                  +                                                            s                      ⁡                                              (                                                                              C                            A                                                    +                                                      C                            0                                                                          )                                                              ⁢                                          R                      0                                                        +                                                            s                      2                                        ⁢                                                                                            C                          A                                                ⁢                                                  C                          0                                                ⁢                                                  R                          0                                                                                            gm                        A                                                                                            ]                                                                        (                  EQ          .                                          ⁢          2                )            Solving the more general expression (EQ. 2) it can be seen that as C0 decreases, the roots P2, P3 move closer in frequency and eventually conjugate, determining as a result, a small phase margin and poor loop stabilization.
FIG. 3 illustrates bode plot 300 and a root locus plot 310 of the open loop response of the cascaded compensation loop inside the prior art amplifier circuit 100 of FIG. 1 with an output capacitor C0 value of 1 pF. Bode plot 300 shows gain AA and GBW greater than bode plot 200 of FIG. 2. A frequency indicated by line 303 shows a point 304 where the gain response 301 crosses 0 dB and point 305 shows the corresponding phase. Bode plot 300 shows a phase margin of 28 degrees. The root locus plot shows the movement of the poles and zeros as the loop is closed.
Root locus plot 300 shows poles P2 and P3 forming a conjugate pair. In addition to stability risks associated with poor gain margin at the resonant frequency in closed loop configuration, the system may exhibit some ringing at the output or peaking in the frequency response. Peaking is a sudden undesired increase in gain at a particular frequency. The peaking may degrade the power supply rejection ratio (PSRR) of the amplifier circuit 100.
Thus, it would be desirable to provide improved compensation that is less sensitive to variations in output capacitance. The present invention solves these and other problems by providing cascode compensation circuit and method for amplifier stability.